Systems on chip (SoC) and processor design teams are challenged to meet aggressive power, performance and area requirements. As chip complexity grows, teams must verify thousands of lines of code to ...

In this paper, we examine the need for formal sequential equivalence checking across pairs of RTL models. We present scenarios that call for modifying the sequential behavior of RTL models while ...

For electronic system-level (ESL) methodologies to come to fruition, designers need to be able to nimbly move between levels of abstraction, especially when it comes to sequential logic. Design is ...

Different design approaches, techniques, and architectures are widely used for synchronous sequential machines. In particular, the micro-programmed machine approach offers important features such as ...